From c39552375661e495b344e8386649ade92a4d45b2 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 7 Dec 2022 19:18:04 -0600
Subject: Implement single-stepping

---
 rtl/core/fetch/prefetch.sv | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'rtl/core/fetch/prefetch.sv')

diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
index 2f0a866..1b5a4c5 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/fetch/prefetch.sv
@@ -13,15 +13,17 @@ module core_prefetch
 
 	output word  insn,
 	output ptr   insn_pc,
-	             next_pc,
-	output logic fetch
+	output logic fetch,
+	             nop
 );
 
 	localparam SIZE = (1 << ORDER) - 1;
 
+	ptr next_pc;
 	logic[31:0] prefetch[SIZE];
 	logic[ORDER - 1:0] valid;
 
+	assign nop = flush ? 1 : ~|valid;
 	assign insn = flush ? `NOP : prefetch[0];
 	assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc;
 	assign fetch = !stall || ~&valid;
-- 
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