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authorAlejandro Soto <alejandro@34project.org>2022-11-09 09:25:48 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-09 09:25:48 -0600
commit5d798386c3b1c1dc45a2fbc382c9367ccc27c524 (patch)
treea04fff74505af30c8044f80f523fd887331e6234 /rtl/core/fetch/fetch.sv
parent65590be80332d132d7037bfe3bb19e5d6e5bcd7b (diff)
Implement reset
Diffstat (limited to '')
-rw-r--r--rtl/core/fetch/fetch.sv18
1 files changed, 9 insertions, 9 deletions
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
index bb52443..dc97909 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/fetch/fetch.sv
@@ -4,6 +4,7 @@ module core_fetch
#(parameter PREFETCH_ORDER=2)
(
input logic clk,
+ rst_n,
stall,
branch,
fetched,
@@ -49,14 +50,13 @@ module core_fetch
addr = hold_addr;
end
- always_ff @(posedge clk) begin
- discard <= discard ? !fetched : flush && fetch;
- hold_addr <= addr;
- end
-
- initial begin
- discard = 0;
- hold_addr = 0;
- end
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ discard <= 0;
+ hold_addr <= 0;
+ end else begin
+ discard <= discard ? !fetched : flush && fetch;
+ hold_addr <= addr;
+ end
endmodule