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authorAlejandro Soto <alejandro@34project.org>2023-09-29 19:50:01 -0600
committerAlejandro Soto <alejandro@34project.org>2023-09-29 20:51:28 -0600
commitbc98bc905c2e796f0d587719196f7e4bf344510a (patch)
treef5859d0b2f4fd5ab8c785a7cbaffa54dc81bc797 /rtl/core/cp15/cache_ops.sv
parentf06c23ac1327850eeeb390e155bfc6330d302a77 (diff)
platform: add CPUs and caches to qsys
Diffstat (limited to 'rtl/core/cp15/cache_ops.sv')
-rw-r--r--rtl/core/cp15/cache_ops.sv15
1 files changed, 15 insertions, 0 deletions
diff --git a/rtl/core/cp15/cache_ops.sv b/rtl/core/cp15/cache_ops.sv
new file mode 100644
index 0000000..cb6d4ad
--- /dev/null
+++ b/rtl/core/cp15/cache_ops.sv
@@ -0,0 +1,15 @@
+`include "core/uarch.sv"
+
+module core_cp15_cache
+(
+ input logic clk,
+ rst_n,
+
+ input logic load,
+ transfer,
+ input word write
+);
+
+ //TODO
+
+endmodule