diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-10 10:11:33 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-10 10:11:33 -0600 |
| commit | acca3eb31a051f335c51306786bb972c21634998 (patch) | |
| tree | 9f8fc3da1a8494e88c5043735862e56c54356bc0 /rtl/core/control | |
| parent | 0f89db514bd174def590645c30a7bd358ea6be93 (diff) | |
Fix reset glitches
Diffstat (limited to 'rtl/core/control')
| -rw-r--r-- | rtl/core/control/data.sv | 5 | ||||
| -rw-r--r-- | rtl/core/control/ldst/ldst.sv | 2 | ||||
| -rw-r--r-- | rtl/core/control/writeback.sv | 2 |
3 files changed, 5 insertions, 4 deletions
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv index fc936dc..0824eac 100644 --- a/rtl/core/control/data.sv +++ b/rtl/core/control/data.sv @@ -69,6 +69,7 @@ module core_control_data c_in <= 0; shifter <= {$bits(shifter){1'b0}}; data_imm <= {$bits(data_imm){1'b0}}; + saved_base <= 0; data_shift_imm <= {$bits(data_shift_imm){1'b0}}; data_snd_is_imm <= 0; data_snd_shift_by_reg <= 0; @@ -77,10 +78,10 @@ module core_control_data alu <= dec.data.op; c_in <= flags.c; - data_snd_is_imm <= dec.snd.is_imm; - data_snd_shift_by_reg <= dec.snd.shift_by_reg; data_imm <= dec.snd.imm; data_shift_imm <= dec.snd.shift_imm; + data_snd_is_imm <= dec.snd.is_imm; + data_snd_shift_by_reg <= dec.snd.shift_by_reg; shifter.shr <= dec.snd.shr; shifter.ror <= dec.snd.ror; diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index baf0054..ef91775 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -52,9 +52,9 @@ module core_control_ldst ldst_increment <= 0; mem_addr <= {$bits(mem_addr){1'b0}}; + mem_regs <= {$bits(mem_regs){1'b0}}; mem_write <= 0; mem_start <= 0; - mem_regs <= {$bits(mem_regs){1'b0}}; mem_offset <= 0; end else unique case(next_cycle) ISSUE: begin diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 1fb3ced..74eb47c 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -144,7 +144,7 @@ module core_control_writeback update_flags <= final_update_flags; EXCEPTION: - final_update_flags <= 0; + update_flags <= 0; endcase unique case(next_cycle) |