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authorAlejandro Soto <alejandro@34project.org>2022-12-11 14:48:08 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-16 16:27:20 -0600
commitff71bcd0c5425c168f111b8f4a92d0a90a6c9c31 (patch)
tree41190239b9220db09d8849afb6d6f6dbbc03f59b /rtl/core/control/writeback.sv
parent6fee344b754464b1fd17f7c0429e6597e51dc74d (diff)
Implement data aborts
Diffstat (limited to 'rtl/core/control/writeback.sv')
-rw-r--r--rtl/core/control/writeback.sv4
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 3bacb75..a7738fb 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -17,7 +17,7 @@ module core_control_writeback
input ctrl_cycle cycle,
next_cycle,
input word saved_base,
- vector,
+ exception_vector,
psr_wb,
coproc_wb,
input reg_num ra,
@@ -81,7 +81,7 @@ module core_control_writeback
end else if(next_cycle.base_writeback)
wr_value = ldst_read;
else if(next_cycle.exception)
- wr_value = vector;
+ wr_value = exception_vector;
else if(next_cycle.mul_hi_wb)
wr_value = mul_q_hi;