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authorAlejandro Soto <alejandro@34project.org>2022-12-09 00:32:34 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-09 00:36:44 -0600
commitb2b2d5124db13714ed82181c9558568d908dfa2a (patch)
tree1779e0751eb49b1a62beff291792455a7e4ff740 /rtl/core/control/writeback.sv
parent2cbccf921bf84665c55cea67b81f31c66dde4249 (diff)
Implement cp15 control
Diffstat (limited to 'rtl/core/control/writeback.sv')
-rw-r--r--rtl/core/control/writeback.sv3
1 files changed, 3 insertions, 0 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 824d867..3bacb75 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -19,6 +19,7 @@ module core_control_writeback
input word saved_base,
vector,
psr_wb,
+ coproc_wb,
input reg_num ra,
popped,
mul_r_add_hi,
@@ -68,6 +69,8 @@ module core_control_writeback
wr_value = mul_q_lo;
else if(cycle.psr)
wr_value = psr_wb;
+ else if(cycle.coproc)
+ wr_value = coproc_wb;
else
// Ruta combinacional larga
wr_value = q_alu;