From b2b2d5124db13714ed82181c9558568d908dfa2a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Fri, 9 Dec 2022 00:32:34 -0600 Subject: Implement cp15 control --- rtl/core/control/writeback.sv | 3 +++ 1 file changed, 3 insertions(+) (limited to 'rtl/core/control/writeback.sv') diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 824d867..3bacb75 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -19,6 +19,7 @@ module core_control_writeback input word saved_base, vector, psr_wb, + coproc_wb, input reg_num ra, popped, mul_r_add_hi, @@ -68,6 +69,8 @@ module core_control_writeback wr_value = mul_q_lo; else if(cycle.psr) wr_value = psr_wb; + else if(cycle.coproc) + wr_value = coproc_wb; else // Ruta combinacional larga wr_value = q_alu; -- cgit v1.2.3