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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-06 19:55:54 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-06 19:55:54 -0600 |
| commit | 8315f5f3ea43150d250aa16575ab274913f93d2a (patch) | |
| tree | d9878fa38b8db2467f768ccd4e2d57012505b29d /rtl/core/control/writeback.sv | |
| parent | 3576202083fb46fb755ceaefb5efe228afa9e2de (diff) | |
Add PSR control signal set
Diffstat (limited to 'rtl/core/control/writeback.sv')
| -rw-r--r-- | rtl/core/control/writeback.sv | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 15b17ee..85b2f9f 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -5,6 +5,7 @@ module core_control_writeback input logic clk, input datapath_decode dec, + input psr_decode dec_psr, input data_decode dec_data, input ctrl_cycle cycle, @@ -102,7 +103,7 @@ module core_control_writeback unique0 case(next_cycle) ISSUE: - final_update_flags <= issue && dec.update_flags; + final_update_flags <= issue && dec_psr.update_flags; EXCEPTION: final_update_flags <= 0; |