From 8315f5f3ea43150d250aa16575ab274913f93d2a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 6 Nov 2022 19:55:54 -0600 Subject: Add PSR control signal set --- rtl/core/control/writeback.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'rtl/core/control/writeback.sv') diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 15b17ee..85b2f9f 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -5,6 +5,7 @@ module core_control_writeback input logic clk, input datapath_decode dec, + input psr_decode dec_psr, input data_decode dec_data, input ctrl_cycle cycle, @@ -102,7 +103,7 @@ module core_control_writeback unique0 case(next_cycle) ISSUE: - final_update_flags <= issue && dec.update_flags; + final_update_flags <= issue && dec_psr.update_flags; EXCEPTION: final_update_flags <= 0; -- cgit v1.2.3