diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-16 16:46:52 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-16 17:55:27 -0600 |
| commit | 683352ce030923bdef3cf4fe90d6cb73f4f74529 (patch) | |
| tree | 09bfdff34626fe90a10d93df2c293f7d87763e44 /rtl/core/control/writeback.sv | |
| parent | 14a3611e492d2f213e81c9053bf613a5d8ad30a6 (diff) | |
Implement psr read/write logic
Diffstat (limited to 'rtl/core/control/writeback.sv')
| -rw-r--r-- | rtl/core/control/writeback.sv | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index f28e9a9..824d867 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -18,6 +18,7 @@ module core_control_writeback next_cycle, input word saved_base, vector, + psr_wb, input reg_num ra, popped, mul_r_add_hi, @@ -65,6 +66,8 @@ module core_control_writeback wr_value = saved_base; else if(cycle.mul || cycle.mul_hi_wb) wr_value = mul_q_lo; + else if(cycle.psr) + wr_value = psr_wb; else // Ruta combinacional larga wr_value = q_alu; |