From 683352ce030923bdef3cf4fe90d6cb73f4f74529 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 16 Nov 2022 16:46:52 -0600 Subject: Implement psr read/write logic --- rtl/core/control/writeback.sv | 3 +++ 1 file changed, 3 insertions(+) (limited to 'rtl/core/control/writeback.sv') diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index f28e9a9..824d867 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -18,6 +18,7 @@ module core_control_writeback next_cycle, input word saved_base, vector, + psr_wb, input reg_num ra, popped, mul_r_add_hi, @@ -65,6 +66,8 @@ module core_control_writeback wr_value = saved_base; else if(cycle.mul || cycle.mul_hi_wb) wr_value = mul_q_lo; + else if(cycle.psr) + wr_value = psr_wb; else // Ruta combinacional larga wr_value = q_alu; -- cgit v1.2.3