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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-15 18:32:55 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-15 18:32:55 -0600 |
| commit | a055bc85bc50897644e7ed62699abff46d818d5f (patch) | |
| tree | 3f6bad895db229e3f004affa057967c2c0e1ea25 /rtl/core/control/select.sv | |
| parent | 5e8bafd124266be27532fc947e246eef35e45789 (diff) | |
Rewrite duplicate ldst logic as signal ldst_next
Diffstat (limited to 'rtl/core/control/select.sv')
| -rw-r--r-- | rtl/core/control/select.sv | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index ee63b42..3cc0ca5 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -7,10 +7,10 @@ module core_control_select input insn_decode dec, - input ctrl_cycle cycle, - next_cycle, + input ctrl_cycle next_cycle, input logic mem_ready, pop_valid, + ldst_next, input reg_num popped, final_rd, mul_r_add_lo, @@ -33,7 +33,7 @@ module core_control_select ra = dec.data.rn; rb = dec.snd.r; end else if(next_cycle.transfer) begin - if(!cycle.transfer || mem_ready) + if(ldst_next) // final_rd viene de dec.ldst.rd rb = pop_valid ? popped : final_rd; end else if(next_cycle.mul_acc_ld) begin |