From a055bc85bc50897644e7ed62699abff46d818d5f Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 15 Nov 2022 18:32:55 -0600 Subject: Rewrite duplicate ldst logic as signal ldst_next --- rtl/core/control/select.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'rtl/core/control/select.sv') diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index ee63b42..3cc0ca5 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -7,10 +7,10 @@ module core_control_select input insn_decode dec, - input ctrl_cycle cycle, - next_cycle, + input ctrl_cycle next_cycle, input logic mem_ready, pop_valid, + ldst_next, input reg_num popped, final_rd, mul_r_add_lo, @@ -33,7 +33,7 @@ module core_control_select ra = dec.data.rn; rb = dec.snd.r; end else if(next_cycle.transfer) begin - if(!cycle.transfer || mem_ready) + if(ldst_next) // final_rd viene de dec.ldst.rd rb = pop_valid ? popped : final_rd; end else if(next_cycle.mul_acc_ld) begin -- cgit v1.2.3