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authorAlejandro Soto <alejandro@34project.org>2022-11-16 16:46:52 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-16 17:55:27 -0600
commit683352ce030923bdef3cf4fe90d6cb73f4f74529 (patch)
tree09bfdff34626fe90a10d93df2c293f7d87763e44 /rtl/core/control/select.sv
parent14a3611e492d2f213e81c9053bf613a5d8ad30a6 (diff)
Implement psr read/write logic
Diffstat (limited to 'rtl/core/control/select.sv')
-rw-r--r--rtl/core/control/select.sv5
1 files changed, 1 insertions, 4 deletions
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 3cc0ca5..1ea2c31 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -17,14 +17,11 @@ module core_control_select
mul_r_add_hi,
output reg_num ra,
- rb,
- output psr_mode reg_mode
+ rb
);
reg_num r_shift, last_ra, last_rb;
- assign reg_mode = `MODE_SVC; //TODO
-
always_comb begin
ra = last_ra;
rb = last_rb;