From 683352ce030923bdef3cf4fe90d6cb73f4f74529 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 16 Nov 2022 16:46:52 -0600 Subject: Implement psr read/write logic --- rtl/core/control/select.sv | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'rtl/core/control/select.sv') diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index 3cc0ca5..1ea2c31 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -17,14 +17,11 @@ module core_control_select mul_r_add_hi, output reg_num ra, - rb, - output psr_mode reg_mode + rb ); reg_num r_shift, last_ra, last_rb; - assign reg_mode = `MODE_SVC; //TODO - always_comb begin ra = last_ra; rb = last_rb; -- cgit v1.2.3