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authorAlejandro Soto <alejandro@34project.org>2022-11-12 21:47:54 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-13 05:54:44 -0600
commit6cb000adf57d7af2ec4aac8fd93d12f09cc63556 (patch)
tree39610a5bd40d8fbb5b0ffd54252113f859dc3c71 /rtl/core/control/issue.sv
parent6281f45ac01e113f2b59fe6f49baad0cc8ab16fc (diff)
Implement CPU halt
Diffstat (limited to 'rtl/core/control/issue.sv')
-rw-r--r--rtl/core/control/issue.sv3
1 files changed, 2 insertions, 1 deletions
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index e3eb338..b2ee6e5 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -4,6 +4,7 @@ module core_control_issue
(
input logic clk,
rst_n,
+ halt,
input insn_decode dec,
input ptr insn_pc,
@@ -22,7 +23,7 @@ module core_control_issue
next_pc_visible
);
- assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
+ assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble && !halt;
assign next_pc_visible = insn_pc + 2;
always_ff @(posedge clk or negedge rst_n)