From 6cb000adf57d7af2ec4aac8fd93d12f09cc63556 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 12 Nov 2022 21:47:54 -0600 Subject: Implement CPU halt --- rtl/core/control/issue.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'rtl/core/control/issue.sv') diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index e3eb338..b2ee6e5 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -4,6 +4,7 @@ module core_control_issue ( input logic clk, rst_n, + halt, input insn_decode dec, input ptr insn_pc, @@ -22,7 +23,7 @@ module core_control_issue next_pc_visible ); - assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble; + assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble && !halt; assign next_pc_visible = insn_pc + 2; always_ff @(posedge clk or negedge rst_n) -- cgit v1.2.3