diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-13 05:22:23 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-13 05:54:44 -0600 |
| commit | d463acba5f9589085afb3dcc4058d82908ff90f2 (patch) | |
| tree | e4ba47f2f9daa8e25b5c244f7af934ff18b54cbc /rtl/core/control/issue.sv | |
| parent | 6cb000adf57d7af2ec4aac8fd93d12f09cc63556 (diff) | |
Convert core state machines to Quartus-inferring RTL
Diffstat (limited to 'rtl/core/control/issue.sv')
| -rw-r--r-- | rtl/core/control/issue.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index b2ee6e5..c1c932e 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -23,7 +23,7 @@ module core_control_issue next_pc_visible ); - assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble && !halt; + assign issue = next_cycle.issue && dec.ctrl.execute && !next_bubble && !halt; assign next_pc_visible = insn_pc + 2; always_ff @(posedge clk or negedge rst_n) @@ -31,7 +31,7 @@ module core_control_issue pc <= 0; undefined <= 0; pc_visible <= 2; - end else if(next_cycle == ISSUE) begin + end else if(next_cycle.issue) begin undefined <= dec.ctrl.undefined; `ifdef VERILATOR |