From d463acba5f9589085afb3dcc4058d82908ff90f2 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 13 Nov 2022 05:22:23 -0600 Subject: Convert core state machines to Quartus-inferring RTL --- rtl/core/control/issue.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'rtl/core/control/issue.sv') diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index b2ee6e5..c1c932e 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -23,7 +23,7 @@ module core_control_issue next_pc_visible ); - assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble && !halt; + assign issue = next_cycle.issue && dec.ctrl.execute && !next_bubble && !halt; assign next_pc_visible = insn_pc + 2; always_ff @(posedge clk or negedge rst_n) @@ -31,7 +31,7 @@ module core_control_issue pc <= 0; undefined <= 0; pc_visible <= 2; - end else if(next_cycle == ISSUE) begin + end else if(next_cycle.issue) begin undefined <= dec.ctrl.undefined; `ifdef VERILATOR -- cgit v1.2.3