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authorAlejandro Soto <alejandro@34project.org>2022-12-14 22:26:37 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-16 16:29:10 -0600
commitae7fd6a060c9bb1ce9db83f8eb23fa19e8fa0e7a (patch)
tree83a1075065c5529a667941df077cf9ba8d664149 /rtl/core/control/issue.sv
parentef151fffb14eac19a19121dfb4c1e015e7470038 (diff)
Implement branch history (simulation only)
Diffstat (limited to '')
-rw-r--r--rtl/core/control/issue.sv27
1 files changed, 26 insertions, 1 deletions
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index 23ecdcf..5bd03e1 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -4,7 +4,9 @@ module core_control_issue
(
input logic clk,
rst_n,
- halt,
+
+ input logic halt,
+ irq,
input insn_decode dec,
input ptr insn_pc,
@@ -27,6 +29,13 @@ module core_control_issue
logic valid;
+`ifdef VERILATOR
+ word bh0 /*verilator public*/,
+ bh1 /*verilator public*/,
+ bh2 /*verilator public*/,
+ bh3 /*verilator public*/;
+`endif
+
assign valid = !next_bubble && !halt;
assign issue = next_cycle.issue && dec.ctrl.execute && valid;
assign next_pc_visible = insn_pc + 2;
@@ -37,6 +46,13 @@ module core_control_issue
undefined <= 0;
pc_visible <= 2;
prefetch_abort <= 0;
+
+`ifdef VERILATOR
+ bh0 <= 0;
+ bh1 <= 0;
+ bh2 <= 0;
+ bh3 <= 0;
+`endif
end else if(next_cycle.issue) begin
if(valid) begin
undefined <= dec.ctrl.undefined;
@@ -50,6 +66,15 @@ module core_control_issue
pc <= insn_pc;
pc_visible <= next_pc_visible;
+
+`ifdef VERILATOR
+ if(insn_pc != pc && insn_pc != pc + 1) begin
+ bh0 <= {pc, 2'b00};
+ bh1 <= bh0;
+ bh2 <= bh1;
+ bh3 <= bh2;
+ end
+`endif
end
endmodule