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| author | Alejandro Soto <alejandro@34project.org> | 2022-12-10 19:56:19 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-10 19:56:19 -0600 |
| commit | 6b163a88179ac3073d22622be4991f332529c8bd (patch) | |
| tree | 5333acb096d9af9a95a40c1b7703bc087134e3fa /rtl/core/control/exception.sv | |
| parent | 8026947ecdf9b023c3720b26bf257bf46f7a2805 (diff) | |
Expose cp15 signals to core toplevel
Diffstat (limited to 'rtl/core/control/exception.sv')
| -rw-r--r-- | rtl/core/control/exception.sv | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv index c4f3772..3965114 100644 --- a/rtl/core/control/exception.sv +++ b/rtl/core/control/exception.sv @@ -6,24 +6,20 @@ module core_control_exception rst_n, input logic undefined, + high_vectors, output word vector, output logic exception ); - logic high_vectors; logic[2:0] vector_offset; assign exception = undefined; //TODO - assign high_vectors = 0; //TODO assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00}; always_comb vector_offset = 3'b001; //TODO - //TODO: spsr_<mode> = cpsr - //TODO: actualizar modo - //TODO: deshabilitar IRQs/FIQs dependiendo de modo //TODO: Considerar que data abort usa + 8, no + 4 endmodule |