From 6b163a88179ac3073d22622be4991f332529c8bd Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 10 Dec 2022 19:56:19 -0600 Subject: Expose cp15 signals to core toplevel --- rtl/core/control/exception.sv | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'rtl/core/control/exception.sv') diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv index c4f3772..3965114 100644 --- a/rtl/core/control/exception.sv +++ b/rtl/core/control/exception.sv @@ -6,24 +6,20 @@ module core_control_exception rst_n, input logic undefined, + high_vectors, output word vector, output logic exception ); - logic high_vectors; logic[2:0] vector_offset; assign exception = undefined; //TODO - assign high_vectors = 0; //TODO assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00}; always_comb vector_offset = 3'b001; //TODO - //TODO: spsr_ = cpsr - //TODO: actualizar modo - //TODO: deshabilitar IRQs/FIQs dependiendo de modo //TODO: Considerar que data abort usa + 8, no + 4 endmodule -- cgit v1.2.3