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authorAlejandro Soto <alejandro@34project.org>2022-12-07 19:18:04 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-07 19:51:41 -0600
commitc39552375661e495b344e8386649ade92a4d45b2 (patch)
tree45623ce35964e43ae7d8804c1ef1c6dedb3ba7a1 /rtl/core/control/debug.sv
parentb1761b8eac5777c09723bbc8cd31cc05d8ec35ae (diff)
Implement single-stepping
Diffstat (limited to '')
-rw-r--r--rtl/core/control/debug.sv25
1 files changed, 25 insertions, 0 deletions
diff --git a/rtl/core/control/debug.sv b/rtl/core/control/debug.sv
new file mode 100644
index 0000000..35b1334
--- /dev/null
+++ b/rtl/core/control/debug.sv
@@ -0,0 +1,25 @@
+`include "core/uarch.sv"
+
+module core_control_debug
+(
+ input logic clk,
+ rst_n,
+ step,
+
+ input ctrl_cycle next_cycle,
+ input logic issue,
+ next_bubble,
+ input insn_decode dec,
+
+ output logic breakpoint
+);
+
+ logic stable, step_trigger;
+
+ assign stable = next_cycle.issue && !dec.ctrl.nop && !next_bubble;
+ assign breakpoint = stable && (dec.ctrl.bkpt || step_trigger);
+
+ always @(posedge clk or negedge rst_n)
+ step_trigger <= !rst_n ? 0 : step && (step_trigger || stable) && !breakpoint;
+
+endmodule