From c39552375661e495b344e8386649ade92a4d45b2 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 7 Dec 2022 19:18:04 -0600 Subject: Implement single-stepping --- rtl/core/control/debug.sv | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 rtl/core/control/debug.sv (limited to 'rtl/core/control/debug.sv') diff --git a/rtl/core/control/debug.sv b/rtl/core/control/debug.sv new file mode 100644 index 0000000..35b1334 --- /dev/null +++ b/rtl/core/control/debug.sv @@ -0,0 +1,25 @@ +`include "core/uarch.sv" + +module core_control_debug +( + input logic clk, + rst_n, + step, + + input ctrl_cycle next_cycle, + input logic issue, + next_bubble, + input insn_decode dec, + + output logic breakpoint +); + + logic stable, step_trigger; + + assign stable = next_cycle.issue && !dec.ctrl.nop && !next_bubble; + assign breakpoint = stable && (dec.ctrl.bkpt || step_trigger); + + always @(posedge clk or negedge rst_n) + step_trigger <= !rst_n ? 0 : step && (step_trigger || stable) && !breakpoint; + +endmodule -- cgit v1.2.3