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authorAlejandro Soto <alejandro@34project.org>2022-11-09 09:25:48 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-09 09:25:48 -0600
commit5d798386c3b1c1dc45a2fbc382c9367ccc27c524 (patch)
treea04fff74505af30c8044f80f523fd887331e6234 /rtl/core/control/coproc.sv
parent65590be80332d132d7037bfe3bb19e5d6e5bcd7b (diff)
Implement reset
Diffstat (limited to 'rtl/core/control/coproc.sv')
-rw-r--r--rtl/core/control/coproc.sv10
1 files changed, 5 insertions, 5 deletions
diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv
index b0c8bea..a457b0f 100644
--- a/rtl/core/control/coproc.sv
+++ b/rtl/core/control/coproc.sv
@@ -3,6 +3,7 @@
module core_control_coproc
(
input logic clk,
+ rst_n,
input insn_decode dec,
@@ -12,11 +13,10 @@ module core_control_coproc
output logic coproc
);
- always_ff @(posedge clk)
- if(next_cycle == ISSUE && issue)
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n)
+ coproc <= 0;
+ else if(next_cycle == ISSUE && issue)
coproc <= dec.ctrl.coproc;
- initial
- coproc = 0;
-
endmodule