From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 9 Nov 2022 09:25:48 -0600 Subject: Implement reset --- rtl/core/control/coproc.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'rtl/core/control/coproc.sv') diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv index b0c8bea..a457b0f 100644 --- a/rtl/core/control/coproc.sv +++ b/rtl/core/control/coproc.sv @@ -3,6 +3,7 @@ module core_control_coproc ( input logic clk, + rst_n, input insn_decode dec, @@ -12,11 +13,10 @@ module core_control_coproc output logic coproc ); - always_ff @(posedge clk) - if(next_cycle == ISSUE && issue) + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) + coproc <= 0; + else if(next_cycle == ISSUE && issue) coproc <= dec.ctrl.coproc; - initial - coproc = 0; - endmodule -- cgit v1.2.3