rtl: implement exclusive monitor datapath

1 files changed, 2 insertions, 0 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index ed0a1e1..6090f2d 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -25,6 +25,7 @@ module core_control
 	input  logic           c_shifter,
 	                       mem_ready,
 	                       mem_fault,
+	                       mem_ex_fail,
 	input  word            mem_data_rd,
 	input  logic           mul_ready,
 	input  word            mul_q_hi,
@@ -62,6 +63,7 @@ module core_control
 	output logic[3:0]      mem_data_be,
 	output logic           mem_start,
 	                       mem_write,
+	                       mem_ex_lock,
 	                       mem_user,
 	output word            mul_a,
 	                       mul_b,