From 70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 2 Oct 2023 01:46:44 -0600 Subject: rtl: implement exclusive monitor datapath --- rtl/core/control/control.sv | 2 ++ 1 file changed, 2 insertions(+) (limited to 'rtl/core/control/control.sv') diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index ed0a1e1..6090f2d 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -25,6 +25,7 @@ module core_control input logic c_shifter, mem_ready, mem_fault, + mem_ex_fail, input word mem_data_rd, input logic mul_ready, input word mul_q_hi, @@ -62,6 +63,7 @@ module core_control output logic[3:0] mem_data_be, output logic mem_start, mem_write, + mem_ex_lock, mem_user, output word mul_a, mul_b, -- cgit v1.2.3