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authorAlejandro Soto <alejandro@34project.org>2022-10-31 16:05:15 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-01 23:04:24 -0600
commit41b263bb39478393a302b284643a590779902f6c (patch)
tree85a37c65c356aad3303e539228c3c770e166b907 /rtl/core/arm810.sv
parentb171ab92f6f7787ca483b83d4b34bbb97f167896 (diff)
Add MUL control cycle
Diffstat (limited to 'rtl/core/arm810.sv')
-rw-r--r--rtl/core/arm810.sv4
1 files changed, 4 insertions, 0 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 517c8de..6028e91 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -122,6 +122,10 @@ module arm810
.c(c_shifter)
);
+ //TODO
+ logic mul, mul_add, mul_long, mul_signed, mul_ready;
+ assign mul_ready = 1;
+
ptr data_addr;
logic data_start, data_write, data_ready, insn_ready;
word data_data_rd, data_data_wr, insn_data_rd;