From 41b263bb39478393a302b284643a590779902f6c Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 31 Oct 2022 16:05:15 -0600 Subject: Add MUL control cycle --- rtl/core/arm810.sv | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'rtl/core/arm810.sv') diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 517c8de..6028e91 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -122,6 +122,10 @@ module arm810 .c(c_shifter) ); + //TODO + logic mul, mul_add, mul_long, mul_signed, mul_ready; + assign mul_ready = 1; + ptr data_addr; logic data_start, data_write, data_ready, insn_ready; word data_data_rd, data_data_wr, insn_data_rd; -- cgit v1.2.3