rtl/cache: split mem.sv out of cache_control.sv

4 files changed, 130 insertions, 94 deletions

diff --git a/rtl/cache/cache.sv b/rtl/cache/cache.sv
index 1fdecde..3cd71ee 100644
--- a/rtl/cache/cache.sv
+++ b/rtl/cache/cache.sv
@@ -57,16 +57,28 @@ module cache
 		.*
 	);
 
-	word cache_mem_address;
-	line cache_mem_writedata;
-	logic cache_core_waitrequest, cache_mem_waitrequest, cache_mem_read, cache_mem_write,
-	      debug_ready, send, send_read, send_inval, set_reply, lock_line, unlock_line;
+	logic cache_core_waitrequest, debug_ready, send, send_read, send_inval,
+	      set_reply, lock_line, unlock_line, mem_begin, writeback;
 
 	cache_control control
 	(
 		.core_read(cache_core_read),
 		.core_write(cache_core_write),
 		.core_waitrequest(cache_core_waitrequest),
+
+		.*
+	);
+
+	word cache_mem_address;
+	line cache_mem_writedata;
+	logic cache_mem_waitrequest, cache_mem_read, cache_mem_write,
+	      mem_end, mem_read_end, mem_wait;
+
+	addr_tag mem_tag;
+	addr_index mem_index;
+
+	cache_mem mem
+	(
 		.mem_waitrequest(cache_mem_waitrequest),
 		.mem_address(cache_mem_address),
 		.mem_writedata(cache_mem_writedata),
diff --git a/rtl/cache/cache_control.sv b/rtl/cache/cache_control.sv
index 1a5ea5f..7c04847 100644
--- a/rtl/cache/cache_control.sv
+++ b/rtl/cache/cache_control.sv
@@ -2,67 +2,63 @@
 
 module cache_control
 (
-	input  logic       clk,
-	                   rst_n,
+	input  logic      clk,
+	                  rst_n,
 
-	input  addr_tag    core_tag,
-	input  addr_index  core_index,
-	input  logic       core_read,
-	                   core_write,
-	                   core_lock,
-	input  line        core_data_wr,
-	output logic       core_waitrequest,
+	input  addr_tag   core_tag,
+	input  addr_index core_index,
+	input  logic      core_read,
+	                  core_write,
+	                  core_lock,
+	input  line       core_data_wr,
+	output logic      core_waitrequest,
 
-	input  ring_req    in_data,				// lo que se recibe
-	input  logic       in_data_valid,		// este caché está recibiendo
-	output logic       in_data_ready,		// este caché esta listo para recibir
-
-	input  logic       out_data_ready,		// este caché está listo para enviar
-	output ring_req    out_data,			// lo que se envía
-	output logic       out_data_valid,		// este caché está enviando datos
+	output logic      in_data_ready,		// este caché esta listo para recibir
+	input  logic      out_data_ready,		// este caché está listo para enviar
 
 	// Señales para la SRAM
-	input  addr_tag    tag_rd,		// valor de la tag de esa línea
-	input  line        data_rd,		// datos de la línea
-	input  line_state  state_rd,	// estado de la línnea
-
-	output addr_index  index_rd,
-	                   index_wr,
-	output logic       write_data,
-	                   write_state,
-	output addr_tag    tag_wr,
-	output line        data_wr,
-	output line_state  state_wr,
-
-	input  logic       mem_waitrequest,
-	input  line        mem_readdata,
-	output word        mem_address,
-	output logic       mem_read,
-	                   mem_write,
-	output line        mem_writedata,
-
-	input  logic       locked,
-	                   may_send,
-	                   out_stall,
-	                   in_hold_valid,
-	                   last_hop,
-	input  ring_req    in_hold,
-	output logic       send,
-	                   send_read,
-	                   send_inval,
-	                   set_reply,
-	                   lock_line,
-	                   unlock_line,
-
-	input  logic       dbg_write,
-	input  addr_index  debug_index,
-	output logic       debug_ready,
-
-	input  line        monitor_update,
-	input  logic       monitor_commit,
-	output logic       monitor_acquire,
-	                   monitor_fail,
-	                   monitor_release
+	input  addr_tag   tag_rd,		// valor de la tag de esa línea
+	input  line_state state_rd,	// estado de la línnea
+
+	output addr_index index_rd,
+	                  index_wr,
+	output logic      write_data,
+	                  write_state,
+	output addr_tag   tag_wr,
+	output line       data_wr,
+	output line_state state_wr,
+
+	input  line       mem_readdata,
+
+	input  logic      locked,
+	                  may_send,
+	                  out_stall,
+	                  in_hold_valid,
+	                  last_hop,
+	                  mem_end,
+	                  mem_read_end,
+	                  mem_wait,
+	input  ring_req   in_hold,
+	input  addr_tag   mem_tag,
+	input  addr_index mem_index,
+	output logic      send,
+	                  send_read,
+	                  send_inval,
+	                  set_reply,
+	                  lock_line,
+	                  unlock_line,
+	                  mem_begin,
+	                  writeback,
+
+	input  logic      dbg_write,
+	input  addr_index debug_index,
+	output logic      debug_ready,
+
+	input  line       monitor_update,
+	input  logic      monitor_commit,
+	output logic      monitor_acquire,
+	                  monitor_fail,
+	                  monitor_release
 );
 
 	enum int unsigned
@@ -73,17 +69,7 @@ module cache_control
 		REPLY
 	} state, next_state;
 
-	logic accept_snoop, debug, end_reply,
-	      mem_begin, mem_end, mem_read_end, mem_wait, wait_reply,
-	      replace, retry, snoop_hit, writeback;
-
-	addr_tag mem_tag;
-	addr_index mem_index;
-
-	assign mem_end = (mem_read || mem_write) && !mem_waitrequest;
-	assign mem_wait = (mem_read || mem_write) && mem_waitrequest;
-	assign mem_address = {`IO_CACHED, mem_tag, mem_index, 4'b0000};
-	assign mem_read_end = mem_read && !mem_waitrequest;
+	logic accept_snoop, debug, end_reply, wait_reply, replace, retry, snoop_hit;
 
 	/* Desbloquear la línea hasta que la request del core termine garantiza
 	 * avance del sistema completo, en lockstep en el peor caso posible,
@@ -364,10 +350,6 @@ module cache_control
 	always_ff @(posedge clk or negedge rst_n)
 		if (!rst_n) begin
 			wait_reply <= 0;
-
-			mem_read <= 0;
-			mem_write <= 0;
-
 			debug_ready <= 0;
 		end else begin
 			if (send)
@@ -376,24 +358,7 @@ module cache_control
 			if (end_reply || mem_read_end)
 				wait_reply <= 0;
 
-			if (mem_end) begin
-				mem_read <= 0;
-				mem_write <= 0;
-			end
-
-			if (mem_begin) begin
-				mem_read <= !writeback;
-				mem_write <= writeback;
-			end
-
 			debug_ready <= debug;
 		end
 
-	always_ff @(posedge clk)
-		if (mem_begin) begin
-			mem_tag <= writeback ? tag_rd : core_tag;
-			mem_index <= index_wr;
-			mem_writedata <= data_rd;
-		end
-
 endmodule
diff --git a/rtl/cache/mem.sv b/rtl/cache/mem.sv
new file mode 100644
index 0000000..a575d0d
--- /dev/null
+++ b/rtl/cache/mem.sv
@@ -0,0 +1,59 @@
+`include "cache/defs.sv"
+
+module cache_mem
+(
+	input  logic      clk,
+	                  rst_n,
+
+	input  addr_tag   core_tag,
+
+	// Señales para la SRAM
+	input  addr_tag   tag_rd,		// valor de la tag de esa línea
+	input  line       data_rd,		// datos de la línea
+
+	input  addr_index index_wr,
+
+	input  logic      mem_waitrequest,
+	output word       mem_address,
+	output logic      mem_read,
+	                  mem_write,
+	output line       mem_writedata,
+
+	input  logic      mem_begin,
+	                  writeback,
+	output logic      mem_end,
+	                  mem_read_end,
+	                  mem_wait,
+	output addr_tag   mem_tag,
+	output addr_index mem_index
+);
+
+	assign mem_end = (mem_read || mem_write) && !mem_waitrequest;
+	assign mem_wait = (mem_read || mem_write) && mem_waitrequest;
+	assign mem_address = {`IO_CACHED, mem_tag, mem_index, 4'b0000};
+	assign mem_read_end = mem_read && !mem_waitrequest;
+
+	always_ff @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			mem_read <= 0;
+			mem_write <= 0;
+		end else begin
+			if (mem_end) begin
+				mem_read <= 0;
+				mem_write <= 0;
+			end
+
+			if (mem_begin) begin
+				mem_read <= !writeback;
+				mem_write <= writeback;
+			end
+		end
+
+	always_ff @(posedge clk)
+		if (mem_begin) begin
+			mem_tag <= writeback ? tag_rd : core_tag;
+			mem_index <= index_wr;
+			mem_writedata <= data_rd;
+		end
+
+endmodule
diff --git a/rtl/cache/ring.sv b/rtl/cache/ring.sv
index 0fad93d..d934fb7 100644
--- a/rtl/cache/ring.sv
+++ b/rtl/cache/ring.sv
@@ -10,7 +10,7 @@ module cache_ring
 
 	input  ring_req    in_data,				// lo que se recibe
 	input  logic       in_data_valid,		// este caché está recibiendo
-	output logic       in_data_ready,		// este caché esta listo para recibir
+	                   in_data_ready,
 
 	input  logic       out_data_ready,		// este caché está listo para enviar
 	output ring_req    out_data,			// lo que se envía