diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-04 14:19:48 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-04 14:19:48 -0600 |
| commit | a7d92072c0bdc3a3e1c99de64f353e932846bc2a (patch) | |
| tree | cc9af86b65820c3a30cf1d0b0c97e8bfe8fc9b44 /rtl/axi_timer/axi_timer_top.sv | |
| parent | 90cd29d85865bb5a4dbdf791616818b151881883 (diff) | |
rtl/pkt_switch: replace axi_timer example with pkt_switch
Diffstat (limited to 'rtl/axi_timer/axi_timer_top.sv')
| -rw-r--r-- | rtl/axi_timer/axi_timer_top.sv | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/rtl/axi_timer/axi_timer_top.sv b/rtl/axi_timer/axi_timer_top.sv deleted file mode 100644 index 6bd0e2a..0000000 --- a/rtl/axi_timer/axi_timer_top.sv +++ /dev/null @@ -1,45 +0,0 @@ -module axi_timer_top -( - input logic clk, - rst_n, - - input logic[31:0] addr, - input logic avalid, - input logic awrite, - output logic aready, - - input logic wvalid, - input logic[31:0] wdata, - output logic wready, - - input logic rready, - output logic[31:0] rdata, - output logic rvalid, - - output logic irq -); - - axi_bus axi(); - - assign axi.Master.ADDR = addr; - assign axi.Master.AVALID = avalid; - assign axi.Master.AWRITE = awrite; - assign aready = axi.Master.AREADY; - - assign axi.Master.WVALID = wvalid; - assign axi.Master.WDATA = wdata; - assign wready = axi.Master.WREADY; - - assign axi.Master.RREADY = rready; - assign rdata = axi.Master.RDATA; - assign rvalid = axi.Master.RVALID; - - axi_timer timer - ( - .i_clk(clk), - .i_rst_n(rst_n), - .o_IRQ(irq), - .axi_slave(axi.Slave) - ); - -endmodule |
