diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-05 17:38:55 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-05 18:12:08 -0600 |
| commit | ca02833f22b08ceeeff501107371aa6667426115 (patch) | |
| tree | f864c5fc238a292082d2096ce546270badce9f1d /platform/wavelet3d/gfx_clz.sv | |
| parent | 081a8a3ba8bfe036f31da53f9c041a2caa30fce2 (diff) | |
rtl/gfx: rename platform/wavelet3d -> rtl/gfx
Diffstat (limited to 'platform/wavelet3d/gfx_clz.sv')
| -rw-r--r-- | platform/wavelet3d/gfx_clz.sv | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/platform/wavelet3d/gfx_clz.sv b/platform/wavelet3d/gfx_clz.sv deleted file mode 100644 index 8d6f100..0000000 --- a/platform/wavelet3d/gfx_clz.sv +++ /dev/null @@ -1,68 +0,0 @@ -/* Implementación en árbol de count leading zeros (CLZ). - * WIDTH debe ser una potencia de 2. - */ -module gfx_clz -#(int WIDTH = 0) -( - input logic clk, - - input logic[WIDTH - 1:0] value, - output logic[$clog2(WIDTH):0] clz -); - - genvar i; - generate - if (WIDTH <= 1) begin - always_ff @(posedge clk) - clz <= !value; - end else if (WIDTH == 2) begin - always_ff @(posedge clk) - unique case (value) - 2'b00: clz <= 2'b10; - 2'b01: clz <= 2'b01; - 2'b10: clz <= 2'b00; - 2'b11: clz <= 2'b00; - endcase - end else if (WIDTH == 4) begin - // Eficiente en FPGAs con 4-LUTs - always_ff @(posedge clk) - if (value[3]) - clz <= 3'b000; - else if (value[2]) - clz <= 3'b001; - else if (value[1]) - clz <= 3'b010; - else if (value[0]) - clz <= 3'b011; - else - clz <= 3'b100; - end else begin - logic msb_right; - logic[$clog2(WIDTH) - 1:0] clz_left, clz_right; - logic[$clog2(WIDTH) - 2:0] tail_right; - - assign {msb_right, tail_right} = clz_right; - - gfx_clz #(WIDTH / 2) left - ( - .clk(clk), - .clz(clz_left), - .value(value[WIDTH - 1:WIDTH / 2]) - ); - - gfx_clz #(WIDTH / 2) right - ( - .clk(clk), - .clz(clz_right), - .value(value[WIDTH / 2 - 1:0]) - ); - - always_ff @(posedge clk) - if (clz_left[$clog2(WIDTH) - 1]) - clz <= {msb_right, ~msb_right, tail_right}; - else - clz <= {1'b0, clz_left}; - end - endgenerate - -endmodule |
