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authorAlejandro Soto <alejandro@34project.org>2023-10-29 15:35:42 -0600
committerAlejandro Soto <alejandro@34project.org>2023-10-29 16:12:33 -0600
commitadabbf5f30729092a64fa1059bbc7d7b09d6b24e (patch)
tree4a4db581d233bcfda18d5e8f2e5606365d52852c /gfx_hw.tcl
parent98d493f9c80f356cdbc2669150d772e451c3b80e (diff)
rtl/gfx: implement double-buffered scanout
Diffstat (limited to 'gfx_hw.tcl')
-rw-r--r--gfx_hw.tcl31
1 files changed, 29 insertions, 2 deletions
diff --git a/gfx_hw.tcl b/gfx_hw.tcl
index 5d56f44..f53c314 100644
--- a/gfx_hw.tcl
+++ b/gfx_hw.tcl
@@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 20.1
-# Thu Oct 26 01:42:02 GMT 2023
+# Sat Oct 28 21:45:46 GMT 2023
# DO NOT MODIFY
#
# gfx "3D graphics accelerator" v1.0
-# 2023.10.26.01:42:02
+# 2023.10.28.21:45:46
#
#
@@ -52,6 +52,9 @@ add_fileset_file skid_flow.sv SYSTEM_VERILOG PATH rtl/gfx/skid_flow.sv
add_fileset_file skid_buf.sv SYSTEM_VERILOG PATH rtl/gfx/skid_buf.sv
add_fileset_file vec_dot.sv SYSTEM_VERILOG PATH rtl/gfx/vec_dot.sv
add_fileset_file transpose.sv SYSTEM_VERILOG PATH rtl/gfx/transpose.sv
+add_fileset_file gfx_scanout.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_scanout.sv
+add_fileset_file gfx_masks.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_masks.sv
+add_fileset_file gfx_mask_sram.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_mask_sram.sv
#
@@ -165,3 +168,27 @@ add_interface_port mem mem_readdata readdata Input 16
add_interface_port mem mem_writedata writedata Output 16
add_interface_port mem mem_waitrequest waitrequest Input 1
+
+#
+# connection point scan
+#
+add_interface scan avalon_streaming start
+set_interface_property scan associatedClock clock
+set_interface_property scan associatedReset reset_sink
+set_interface_property scan dataBitsPerSymbol 10
+set_interface_property scan errorDescriptor ""
+set_interface_property scan firstSymbolInHighOrderBits true
+set_interface_property scan maxChannel 0
+set_interface_property scan readyLatency 0
+set_interface_property scan ENABLED true
+set_interface_property scan EXPORT_OF ""
+set_interface_property scan PORT_NAME_MAP ""
+set_interface_property scan CMSIS_SVD_VARIABLES ""
+set_interface_property scan SVD_ADDRESS_GROUP ""
+
+add_interface_port scan scan_data data Output 30
+add_interface_port scan scan_endofpacket endofpacket Output 1
+add_interface_port scan scan_ready ready Input 1
+add_interface_port scan scan_startofpacket startofpacket Output 1
+add_interface_port scan scan_valid valid Output 1
+