rtl/core, tb: replace bus_master with a new top-level module

1 files changed, 0 insertions, 159 deletions

diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl
deleted file mode 100644
index a83c642..0000000
--- a/conspiracion_bus_master_hw.tcl
+++ /dev/null
@@ -1,159 +0,0 @@
-# TCL File Generated by Component Editor 20.1
-# Wed Nov 16 05:30:25 GMT 2022
-# DO NOT MODIFY
-
-
-# 
-# conspiracion_bus_master "Toplevel bus master" v1.0
-#  2022.11.16.05:30:25
-# 
-# 
-
-# 
-# request TCL package from ACDS 16.1
-# 
-package require -exact qsys 16.1
-
-
-# 
-# module conspiracion_bus_master
-# 
-set_module_property DESCRIPTION ""
-set_module_property NAME conspiracion_bus_master
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME "Toplevel bus master"
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-# 
-# file sets
-# 
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL bus_master
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file bus_master.sv SYSTEM_VERILOG PATH rtl/bus_master.sv
-
-
-# 
-# parameters
-# 
-
-
-# 
-# display items
-# 
-
-
-# 
-# connection point clock
-# 
-add_interface clock clock end
-set_interface_property clock clockRate 0
-set_interface_property clock ENABLED true
-set_interface_property clock EXPORT_OF ""
-set_interface_property clock PORT_NAME_MAP ""
-set_interface_property clock CMSIS_SVD_VARIABLES ""
-set_interface_property clock SVD_ADDRESS_GROUP ""
-
-add_interface_port clock clk clk Input 1
-
-
-# 
-# connection point reset_sink
-# 
-add_interface reset_sink reset end
-set_interface_property reset_sink associatedClock clock
-set_interface_property reset_sink synchronousEdges DEASSERT
-set_interface_property reset_sink ENABLED true
-set_interface_property reset_sink EXPORT_OF ""
-set_interface_property reset_sink PORT_NAME_MAP ""
-set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
-set_interface_property reset_sink SVD_ADDRESS_GROUP ""
-
-add_interface_port reset_sink rst_n reset_n Input 1
-
-
-# 
-# connection point core
-# 
-add_interface core conduit end
-set_interface_property core associatedClock clock
-set_interface_property core associatedReset reset_sink
-set_interface_property core ENABLED true
-set_interface_property core EXPORT_OF ""
-set_interface_property core PORT_NAME_MAP ""
-set_interface_property core CMSIS_SVD_VARIABLES ""
-set_interface_property core SVD_ADDRESS_GROUP ""
-
-add_interface_port core addr addr Input 30
-add_interface_port core data_rd data_rd Output 32
-add_interface_port core data_wr data_wr Input 32
-add_interface_port core ready ready Output 1
-add_interface_port core write write Input 1
-add_interface_port core start start Input 1
-add_interface_port core irq irq Output 1
-add_interface_port core cpu_clk cpu_clk Output 1
-add_interface_port core cpu_rst_n cpu_rst_n Output 1
-add_interface_port core data_be data_be Input 4
-
-
-# 
-# connection point irq
-# 
-add_interface irq interrupt start
-set_interface_property irq associatedAddressablePoint avalon_master_1_1
-set_interface_property irq associatedClock clock
-set_interface_property irq associatedReset reset_sink
-set_interface_property irq irqScheme INDIVIDUAL_REQUESTS
-set_interface_property irq ENABLED true
-set_interface_property irq EXPORT_OF ""
-set_interface_property irq PORT_NAME_MAP ""
-set_interface_property irq CMSIS_SVD_VARIABLES ""
-set_interface_property irq SVD_ADDRESS_GROUP ""
-
-add_interface_port irq avl_irq irq Input 1
-
-
-# 
-# connection point avalon_master_1_1
-# 
-add_interface avalon_master_1_1 avalon start
-set_interface_property avalon_master_1_1 addressUnits SYMBOLS
-set_interface_property avalon_master_1_1 associatedClock clock
-set_interface_property avalon_master_1_1 associatedReset reset_sink
-set_interface_property avalon_master_1_1 bitsPerSymbol 8
-set_interface_property avalon_master_1_1 burstOnBurstBoundariesOnly false
-set_interface_property avalon_master_1_1 burstcountUnits WORDS
-set_interface_property avalon_master_1_1 doStreamReads false
-set_interface_property avalon_master_1_1 doStreamWrites false
-set_interface_property avalon_master_1_1 holdTime 0
-set_interface_property avalon_master_1_1 linewrapBursts false
-set_interface_property avalon_master_1_1 maximumPendingReadTransactions 0
-set_interface_property avalon_master_1_1 maximumPendingWriteTransactions 0
-set_interface_property avalon_master_1_1 readLatency 0
-set_interface_property avalon_master_1_1 readWaitTime 1
-set_interface_property avalon_master_1_1 setupTime 0
-set_interface_property avalon_master_1_1 timingUnits Cycles
-set_interface_property avalon_master_1_1 writeWaitTime 0
-set_interface_property avalon_master_1_1 ENABLED true
-set_interface_property avalon_master_1_1 EXPORT_OF ""
-set_interface_property avalon_master_1_1 PORT_NAME_MAP ""
-set_interface_property avalon_master_1_1 CMSIS_SVD_VARIABLES ""
-set_interface_property avalon_master_1_1 SVD_ADDRESS_GROUP ""
-
-add_interface_port avalon_master_1_1 avl_address address Output 32
-add_interface_port avalon_master_1_1 avl_read read Output 1
-add_interface_port avalon_master_1_1 avl_readdata readdata Input 32
-add_interface_port avalon_master_1_1 avl_write write Output 1
-add_interface_port avalon_master_1_1 avl_writedata writedata Output 32
-add_interface_port avalon_master_1_1 avl_byteenable byteenable Output 4
-add_interface_port avalon_master_1_1 avl_waitrequest waitrequest Input 1
-