diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-12 21:25:37 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-13 05:54:44 -0600 |
| commit | 9a1dd87d89d3cb57fe0d811e462b9348234eae79 (patch) | |
| tree | f93aa77748527ecedcc18bae629b8d81a7eb0a4d /conspiracion_bus_master_hw.tcl | |
| parent | 7d171c1e3ae6dab855ee264e7926281c3a4d25ca (diff) | |
Route cpu_rst_n signal through bus master
Diffstat (limited to 'conspiracion_bus_master_hw.tcl')
| -rw-r--r-- | conspiracion_bus_master_hw.tcl | 73 |
1 files changed, 37 insertions, 36 deletions
diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl index f7f9760..2cb7f85 100644 --- a/conspiracion_bus_master_hw.tcl +++ b/conspiracion_bus_master_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Wed Nov 09 13:54:58 GMT 2022 +# Sat Nov 12 23:28:38 GMT 2022 # DO NOT MODIFY # # conspiracion_bus_master "Toplevel bus master" v1.0 -# 2022.11.09.13:54:58 +# 2022.11.12.23:28:37 # # @@ -101,13 +101,14 @@ add_interface_port core write write Input 1 add_interface_port core start start Input 1 add_interface_port core irq irq Output 1 add_interface_port core cpu_clk cpu_clk Output 1 +add_interface_port core cpu_rst_n cpu_rst_n Output 1 # # connection point irq # add_interface irq interrupt start -set_interface_property irq associatedAddressablePoint avalon_master_1 +set_interface_property irq associatedAddressablePoint avalon_master_1_1 set_interface_property irq associatedClock clock set_interface_property irq associatedReset reset_sink set_interface_property irq irqScheme INDIVIDUAL_REQUESTS @@ -121,37 +122,37 @@ add_interface_port irq avl_irq irq Input 1 # -# connection point avalon_master_1 -# -add_interface avalon_master_1 avalon start -set_interface_property avalon_master_1 addressUnits SYMBOLS -set_interface_property avalon_master_1 associatedClock clock -set_interface_property avalon_master_1 associatedReset reset_sink -set_interface_property avalon_master_1 bitsPerSymbol 8 -set_interface_property avalon_master_1 burstOnBurstBoundariesOnly false -set_interface_property avalon_master_1 burstcountUnits WORDS -set_interface_property avalon_master_1 doStreamReads false -set_interface_property avalon_master_1 doStreamWrites false -set_interface_property avalon_master_1 holdTime 0 -set_interface_property avalon_master_1 linewrapBursts false -set_interface_property avalon_master_1 maximumPendingReadTransactions 0 -set_interface_property avalon_master_1 maximumPendingWriteTransactions 0 -set_interface_property avalon_master_1 readLatency 0 -set_interface_property avalon_master_1 readWaitTime 1 -set_interface_property avalon_master_1 setupTime 0 -set_interface_property avalon_master_1 timingUnits Cycles -set_interface_property avalon_master_1 writeWaitTime 0 -set_interface_property avalon_master_1 ENABLED true -set_interface_property avalon_master_1 EXPORT_OF "" -set_interface_property avalon_master_1 PORT_NAME_MAP "" -set_interface_property avalon_master_1 CMSIS_SVD_VARIABLES "" -set_interface_property avalon_master_1 SVD_ADDRESS_GROUP "" - -add_interface_port avalon_master_1 avl_address address Output 32 -add_interface_port avalon_master_1 avl_read read Output 1 -add_interface_port avalon_master_1 avl_readdata readdata Input 32 -add_interface_port avalon_master_1 avl_write write Output 1 -add_interface_port avalon_master_1 avl_writedata writedata Output 32 -add_interface_port avalon_master_1 avl_byteenable byteenable Output 4 -add_interface_port avalon_master_1 avl_waitrequest waitrequest Input 1 +# connection point avalon_master_1_1 +# +add_interface avalon_master_1_1 avalon start +set_interface_property avalon_master_1_1 addressUnits SYMBOLS +set_interface_property avalon_master_1_1 associatedClock clock +set_interface_property avalon_master_1_1 associatedReset reset_sink +set_interface_property avalon_master_1_1 bitsPerSymbol 8 +set_interface_property avalon_master_1_1 burstOnBurstBoundariesOnly false +set_interface_property avalon_master_1_1 burstcountUnits WORDS +set_interface_property avalon_master_1_1 doStreamReads false +set_interface_property avalon_master_1_1 doStreamWrites false +set_interface_property avalon_master_1_1 holdTime 0 +set_interface_property avalon_master_1_1 linewrapBursts false +set_interface_property avalon_master_1_1 maximumPendingReadTransactions 0 +set_interface_property avalon_master_1_1 maximumPendingWriteTransactions 0 +set_interface_property avalon_master_1_1 readLatency 0 +set_interface_property avalon_master_1_1 readWaitTime 1 +set_interface_property avalon_master_1_1 setupTime 0 +set_interface_property avalon_master_1_1 timingUnits Cycles +set_interface_property avalon_master_1_1 writeWaitTime 0 +set_interface_property avalon_master_1_1 ENABLED true +set_interface_property avalon_master_1_1 EXPORT_OF "" +set_interface_property avalon_master_1_1 PORT_NAME_MAP "" +set_interface_property avalon_master_1_1 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_master_1_1 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_master_1_1 avl_address address Output 32 +add_interface_port avalon_master_1_1 avl_read read Output 1 +add_interface_port avalon_master_1_1 avl_readdata readdata Input 32 +add_interface_port avalon_master_1_1 avl_write write Output 1 +add_interface_port avalon_master_1_1 avl_writedata writedata Output 32 +add_interface_port avalon_master_1_1 avl_byteenable byteenable Output 4 +add_interface_port avalon_master_1_1 avl_waitrequest waitrequest Input 1 |