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authorAlejandro Soto <alejandro@34project.org>2023-10-06 08:56:38 -0600
committerAlejandro Soto <alejandro@34project.org>2023-10-06 08:56:38 -0600
commit71df72cbe6fdfd65e5f7e3eb82bbeb76815b1ee7 (patch)
treeda1d4cf1b3902d563b26e5c83f96f5f9c4ffe15b /cache_hw.tcl
parent8d22db83560d782c2f9e43e7359d7f616a3f4bb0 (diff)
rtl/cache: split ring.sv out of cache_control.sv
Diffstat (limited to '')
-rw-r--r--cache_hw.tcl1
1 files changed, 1 insertions, 0 deletions
diff --git a/cache_hw.tcl b/cache_hw.tcl
index 0aa2c2c..181bfe9 100644
--- a/cache_hw.tcl
+++ b/cache_hw.tcl
@@ -42,6 +42,7 @@ set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/cache/cache.sv TOP_LEVEL_FILE
add_fileset_file cache_control.sv SYSTEM_VERILOG PATH rtl/cache/cache_control.sv
add_fileset_file token.sv SYSTEM_VERILOG PATH rtl/cache/token.sv
+add_fileset_file ring.sv SYSTEM_VERILOG PATH rtl/cache/ring.sv
add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv
add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv
add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv