From 71df72cbe6fdfd65e5f7e3eb82bbeb76815b1ee7 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Fri, 6 Oct 2023 08:56:38 -0600 Subject: rtl/cache: split ring.sv out of cache_control.sv --- cache_hw.tcl | 1 + 1 file changed, 1 insertion(+) (limited to 'cache_hw.tcl') diff --git a/cache_hw.tcl b/cache_hw.tcl index 0aa2c2c..181bfe9 100644 --- a/cache_hw.tcl +++ b/cache_hw.tcl @@ -42,6 +42,7 @@ set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/cache/cache.sv TOP_LEVEL_FILE add_fileset_file cache_control.sv SYSTEM_VERILOG PATH rtl/cache/cache_control.sv add_fileset_file token.sv SYSTEM_VERILOG PATH rtl/cache/token.sv +add_fileset_file ring.sv SYSTEM_VERILOG PATH rtl/cache/ring.sv add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv -- cgit v1.2.3