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authorAlejandro Soto <alejandro@34project.org>2023-10-03 07:46:10 -0600
committerAlejandro Soto <alejandro@34project.org>2023-10-03 07:46:10 -0600
commitd9e89db78284fc1a9f0aa1ed86d076f50c58c1f2 (patch)
treee29cef947858a7a1791f3be3280bb43f9212da0a
parentf422a5fd9e83c69d4158a165edc47f45bcf600c4 (diff)
tb/sim: add test: strex
-rw-r--r--tb/sim/strex.S16
-rw-r--r--tb/sim/strex.py9
2 files changed, 25 insertions, 0 deletions
diff --git a/tb/sim/strex.S b/tb/sim/strex.S
new file mode 100644
index 0000000..5ea2b33
--- /dev/null
+++ b/tb/sim/strex.S
@@ -0,0 +1,16 @@
+.global reset
+
+reset:
+ ldr r0, =0x1000
+ ldr r1, =0x01234567
+ str r1, [r0]
+ mvn r1, r1
+ str r1, [r0, #4]
+ strex r2, r0, [r0] @ Debe fallar
+ ldrex r3, [r0]
+ add r0, r0, #4
+ ldrex r4, [r0]
+ strex r5, r3, [r0] @ Debe fallar
+ sub r0, r0, #4
+ strex r6, r4, [r0] @ Debe servir
+ mov pc, lr
diff --git a/tb/sim/strex.py b/tb/sim/strex.py
new file mode 100644
index 0000000..d53c355
--- /dev/null
+++ b/tb/sim/strex.py
@@ -0,0 +1,9 @@
+mem_dumps = [range(0x1000, 0x1008)]
+
+def final():
+ assert_reg(r2, 1)
+ assert_reg(r5, 1)
+ assert_reg(r6, 0)
+
+ assert_mem(0x1000, 0xfedcba98)
+ assert_mem(0x1004, 0x01234567)