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| author | Alejandro Soto <alejandro@34project.org> | 2024-05-23 20:23:55 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-24 05:58:44 -0600 |
| commit | a148430ae145d99ba50a87b6147fa0e6e81cb258 (patch) | |
| tree | 0bf32511c1ce4513c6729a3868ef6b5918bf6c38 | |
| parent | 3195459c67e88af9c70a89e4d456d248e361575c (diff) | |
rtl/wb2axip: fix endianness in axisgdma
| -rw-r--r-- | rtl/wb2axip/axisgdma.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/rtl/wb2axip/axisgdma.v b/rtl/wb2axip/axisgdma.v index 09c38b2..4889151 100644 --- a/rtl/wb2axip/axisgdma.v +++ b/rtl/wb2axip/axisgdma.v @@ -804,7 +804,8 @@ module axisgdma #( // {{{ .C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH), .C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH), - .FETCH_LIMIT(4) + .FETCH_LIMIT(4), + .SWAP_ENDIANNESS(1'b0) // ???? Por qué estaba en 1 ??? // }}} ) pf ( // {{{ |