Split branch logic out of control.sv

3 files changed, 37 insertions, 6 deletions

diff --git a/conspiracion.qsf b/conspiracion.qsf
index d709042..6ec96a1 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -136,6 +136,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/branch.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/control.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/cycles.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/issue.sv
diff --git a/rtl/core/control/branch.sv b/rtl/core/control/branch.sv
new file mode 100644
index 0000000..3f8160e
--- /dev/null
+++ b/rtl/core/control/branch.sv
@@ -0,0 +1,31 @@
+`include "core/uarch.sv"
+
+module core_control_branch
+(
+	input  logic           clk,
+
+	input  datapath_decode dec,
+	input  branch_decode   dec_branch,
+
+	input  ctrl_cycle      next_cycle,
+	input  logic           issue,
+	input  ptr             next_pc_visible,
+
+	output logic           branch,
+	output ptr             branch_target
+);
+
+	always_ff @(posedge clk) begin
+		branch <= 0;
+		if(next_cycle == ISSUE && issue) begin
+			branch <= dec.branch;
+			branch_target <= next_pc_visible + dec_branch.offset;
+		end
+	end
+
+	initial begin
+		branch = 1;
+		branch_target = {$bits(branch_target){1'b0}};
+	end
+
+endmodule
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index faba1c1..0912387 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -106,6 +106,11 @@ module core_control
 		.pop_lower(popped_lower)
 	);
 
+	core_control_branch ctrl_branch
+	(
+		.*
+	);
+
 	core_control_mux ctrl_mux
 	(
 		.*
@@ -123,7 +128,6 @@ module core_control
 		vector_offset = 3'b001; //TODO
 
 	always_ff @(posedge clk) begin
-		branch <= 0;
 		update_flags <= 0;
 		wb_alu_flags <= alu_flags;
 
@@ -132,9 +136,6 @@ module core_control
 				final_update_flags <= 0;
 
 				if(issue) begin
-					branch <= dec.branch;
-					branch_target <= next_pc_visible + dec_branch.offset;
-
 					alu <= dec_data.op;
 					ra <= dec_data.rn;
 
@@ -224,8 +225,6 @@ module core_control
 
 	initial begin
 		c_in = 0;
-		branch = 1;
-		branch_target = 30'd0;
 		data_snd_shift_by_reg = 0;
 
 		wb_alu_flags = 4'b0000;