Move CP15 logic out of control.sv

3 files changed, 29 insertions, 8 deletions

diff --git a/conspiracion.qsf b/conspiracion.qsf
index a9e7fc3..d89cf81 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -138,6 +138,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/branch.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/control.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/coproc.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/cycles.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/data.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/exception.sv
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 49c1e8b..e8a1a69 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -126,15 +126,13 @@ module core_control
 		.*
 	);
 
-	always_ff @(posedge clk) begin
-		wb_alu_flags <= alu_flags;
+	core_control_coproc ctrl_cp
+	(
+		.*
+	);
 
-		unique0 case(next_cycle)
-			ISSUE:
-				if(issue)
-					coproc <= dec.coproc;
-		endcase
-	end
+	always_ff @(posedge clk)
+		wb_alu_flags <= alu_flags;
 
 	initial
 		wb_alu_flags = 4'b0000;
diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv
new file mode 100644
index 0000000..f0b4169
--- /dev/null
+++ b/rtl/core/control/coproc.sv
@@ -0,0 +1,22 @@
+`include "core/uarch.sv"
+
+module core_control_coproc
+(
+	input  logic           clk,
+
+	input  datapath_decode dec,
+
+	input  ctrl_cycle      next_cycle,
+	input  logic           issue,
+
+	output logic           coproc
+);
+
+	always_ff @(posedge clk)
+		if(next_cycle == ISSUE && issue)
+			coproc <= dec.coproc;
+
+	initial
+		coproc = 0;
+
+endmodule