rtl, tb: add core.mk files

15 files changed, 123 insertions, 8 deletions

diff --git a/Makefile b/Makefile
index 8057426..599e507 100644
--- a/Makefile
+++ b/Makefile
@@ -1,3 +1,6 @@
+top := conspiracion
+core_dirs := rtl tb
+
 .PHONY: all
 
 all: test
diff --git a/rtl/cache/mod.mk b/rtl/cache/mod.mk
new file mode 100644
index 0000000..10b7d1a
--- /dev/null
+++ b/rtl/cache/mod.mk
@@ -0,0 +1,5 @@
+define core
+  $(this)/deps     := config
+  $(this)/rtl_dirs := .
+  $(this)/rtl_top  := cache
+endef
diff --git a/rtl/config.sv b/rtl/config.sv
index 684dd6b..6353902 100644
--- a/rtl/config.sv
+++ b/rtl/config.sv
@@ -1,7 +1,7 @@
 `ifndef CONFIG_SV
 `define CONFIG_SV
 
-`define CONFIG_CPUS  1
+`define CONFIG_CPUS  4
 `define CONFIG_CACHE 1
 
 `endif
diff --git a/rtl/core/core_cp15_far.sv b/rtl/core/core_cp15_far.sv
index ca1dcf1..e990c52 100644
--- a/rtl/core/core_cp15_far.sv
+++ b/rtl/core/core_cp15_far.sv
@@ -16,16 +16,17 @@ module core_cp15_far
 	output word      read /*verilator public*/
 );
 
-	word far;
+	// %Warning-SYMRSVDWORD: rtl/core/core_cp15_far.sv:19:7: Symbol matches C++ common word: 'far'
+	word far_;
 
-	assign read = far;
+	assign read = far_;
 
 	always @(posedge clk or negedge rst_n)
 		if(!rst_n)
-			far <= 0;
+			far_ <= 0;
 		else if(fault_register)
-			far <= {fault_addr, 2'b00};
+			far_ <= {fault_addr, 2'b00};
 		else if(transfer && !load)
-			far <= write;
+			far_ <= write;
 
 endmodule
diff --git a/rtl/core/mod.mk b/rtl/core/mod.mk
new file mode 100644
index 0000000..960d1f1
--- /dev/null
+++ b/rtl/core/mod.mk
@@ -0,0 +1,9 @@
+define core
+  $(this)/deps     := config
+  $(this)/rtl_dirs := .
+  $(this)/rtl_top  := core
+
+  ifeq (sim,$(flow/type))
+    $(this)/deps += ip_mul
+  endif
+endef
diff --git a/rtl/gfx/mod.mk b/rtl/gfx/mod.mk
new file mode 100644
index 0000000..4e0f46d
--- /dev/null
+++ b/rtl/gfx/mod.mk
@@ -0,0 +1,5 @@
+define core
+  $(this)/deps     := config
+  $(this)/rtl_dirs := .
+  $(this)/rtl_top  := gfx
+endef
diff --git a/rtl/mod.mk b/rtl/mod.mk
new file mode 100644
index 0000000..ec770a2
--- /dev/null
+++ b/rtl/mod.mk
@@ -0,0 +1,16 @@
+cores   := config debounce intc
+subdirs := cache core gfx perf smp top
+
+define core/config
+  $(this)/rtl_include_dirs := .
+endef
+
+define core/debounce
+  $(this)/rtl_files := debounce.sv
+  $(this)/rtl_top   := debounce
+endef
+
+define core/intc
+  $(this)/rtl_files := intc.sv
+  $(this)/rtl_top   := intc
+endef
diff --git a/rtl/perf/mod.mk b/rtl/perf/mod.mk
new file mode 100644
index 0000000..813301f
--- /dev/null
+++ b/rtl/perf/mod.mk
@@ -0,0 +1,4 @@
+define core
+  $(this)/rtl_dirs := .
+  $(this)/rtl_top  := perf
+endef
diff --git a/rtl/smp/mod.mk b/rtl/smp/mod.mk
new file mode 100644
index 0000000..3c14a30
--- /dev/null
+++ b/rtl/smp/mod.mk
@@ -0,0 +1,4 @@
+define core
+  $(this)/rtl_top := smp_ctrl
+  $(this)/rtl_dirs := .
+endef
diff --git a/rtl/smp/smp_ctrl.sv b/rtl/smp/smp_ctrl.sv
index 2bf812e..b9f3106 100644
--- a/rtl/smp/smp_ctrl.sv
+++ b/rtl/smp/smp_ctrl.sv
@@ -31,6 +31,10 @@ module smp_ctrl
 	                   step_3
 );
 
+`ifdef VERILATOR
+	logic avl_address /*verilator public*/;
+`endif
+
 	logic write;
 	logic[7:0] readdata_3, readdata_2, readdata_1, readdata_0,
 	           writedata_3, writedata_2, writedata_1, writedata_0;
diff --git a/rtl/top/mod.mk b/rtl/top/mod.mk
new file mode 100644
index 0000000..6c6acf2
--- /dev/null
+++ b/rtl/top/mod.mk
@@ -0,0 +1,46 @@
+cores := conspiracion test_fb test_fifo test_ring test_smp
+
+define core/conspiracion
+  $(this)/targets   := sim
+  $(this)/deps      := conspiracion/tb
+  $(this)/rtl_files := conspiracion.sv
+  $(this)/rtl_top   := conspiracion
+  $(this)/vl_main   := ../../tb/top/conspiracion/conspiracion.cpp
+  $(this)/vl_runner := run_conspiracion
+endef
+
+define core/test_fb
+  $(this)/targets        := test
+  $(this)/deps           := gfx
+  $(this)/rtl_files      := test_fb.sv
+  $(this)/rtl_top        := test_fb
+  $(this)/cocotb_paths   := ../../..
+  $(this)/cocotb_modules := tb.top.test_fb
+endef
+
+define core/test_fifo
+  $(this)/targets        := test
+  $(this)/deps           := gfx
+  $(this)/rtl_files      := test_fifo.sv
+  $(this)/rtl_top        := test_fifo
+  $(this)/cocotb_paths   := ../../..
+  $(this)/cocotb_modules := tb.top.test_fifo
+endef
+
+define core/test_ring
+  $(this)/targets        := test
+  $(this)/deps           := cache
+  $(this)/rtl_files      := test_ring.sv
+  $(this)/rtl_top        := test_ring
+  $(this)/cocotb_paths   := ../../..
+  $(this)/cocotb_modules := tb.top.test_ring
+endef
+
+define core/test_smp
+  $(this)/targets        := test
+  $(this)/deps           := smp test_fifo test_ring
+  $(this)/rtl_files      := test_smp.sv
+  $(this)/rtl_top        := test_smp
+  $(this)/cocotb_paths   := ../../..
+  $(this)/cocotb_modules := tb.top.test_smp
+endef
diff --git a/tb/mod.mk b/tb/mod.mk
new file mode 100644
index 0000000..ff445be
--- /dev/null
+++ b/tb/mod.mk
@@ -0,0 +1,10 @@
+cores := ip_mul interconnect
+subdirs := top/conspiracion
+
+define core/ip_mul
+  $(this)/rtl_files := dsp_mul.sv
+endef
+
+define core/interconnect
+  $(this)/rtl_files := mem_interconnect.sv
+endef
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion/conspiracion.cpp
index e1f5f78..e1f5f78 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion/conspiracion.cpp
diff --git a/tb/top/conspiracion/mod.mk b/tb/top/conspiracion/mod.mk
new file mode 100644
index 0000000..d775150
--- /dev/null
+++ b/tb/top/conspiracion/mod.mk
@@ -0,0 +1,8 @@
+cores := conspiracion/tb
+
+define core/conspiracion/tb
+  $(this)/deps         := cache core perf smp interconnect
+  $(this)/rtl_files    := platform.sv sim_slave.sv vga_domain.sv
+  $(this)/vl_files     := interrupt.cpp interval_timer.cpp jtag_uart.cpp mem.cpp sim_slave.cpp
+  $(this)/vl_pkgconfig := ncursesw sdl2
+endef
diff --git a/tb/top/conspiracion/vga_domain.sv b/tb/top/conspiracion/vga_domain.sv
index 0c9aac5..55c564c 100644
--- a/tb/top/conspiracion/vga_domain.sv
+++ b/tb/top/conspiracion/vga_domain.sv
@@ -26,11 +26,11 @@ module vga_domain
 	logic[7:0]  vga_g /*verilator public*/;
 	logic[7:0]  vga_b  /*verilator public*/;
 
-	vga crtc
+	/*vga crtc
 	(
 		.clk(clk_clk),
 		.rst_n(reset_reset_n),
 		.*
-	);
+	);*/
 
 endmodule