rtl/cache: implement wait-for-reply

6 files changed, 28 insertions, 19 deletions

diff --git a/rtl/cache/cache.sv b/rtl/cache/cache.sv
index 6efeb28..b84f844 100644
--- a/rtl/cache/cache.sv
+++ b/rtl/cache/cache.sv
@@ -6,7 +6,7 @@ module cache
 	input  logic    clk,
 	                rst_n,
 
-	input  word     core_address,
+	input  ptr      core_address,
 	input  logic    core_read,
 	                core_write,
 	input  word     core_writedata,
diff --git a/rtl/cache/control.sv b/rtl/cache/control.sv
index f551477..a930e87 100644
--- a/rtl/cache/control.sv
+++ b/rtl/cache/control.sv
@@ -55,9 +55,9 @@ module cache_control
 		REPLY
 	} state, next_state;
 
-	logic accept_snoop, in_hold_valid, last_hop, lock_line, locked, may_send,
-	      may_send_if_token_held, mem_begin, mem_end, mem_end_read, mem_wait,
-	      out_stall, reply_wait, replace, retry, send, send_inval, send_read,
+	logic accept_snoop, in_hold_valid, inval_reply, last_hop, lock_line, locked,
+	      may_send, may_send_if_token_held, mem_begin, mem_end, mem_read_end, mem_wait,
+	      out_stall, wait_reply, replace, retry, send, send_inval, send_read,
 	      snoop_hit, set_reply, unlock_line, writeback;
 
 	ring_req in_hold, send_data, fwd_data, stall_data, out_data_next;
@@ -68,7 +68,7 @@ module cache_control
 	assign mem_end = (mem_read || mem_write) && !mem_waitrequest;
 	assign mem_wait = (mem_read || mem_write) && mem_waitrequest;
 	assign mem_address = {3'b000, mem_tag, mem_index, 4'b0000};
-	assign mem_end_read = mem_read && !mem_waitrequest;
+	assign mem_read_end = mem_read && !mem_waitrequest;
 
 	/* Desbloquear la línea hasta que la request del core termine garantiza
 	 * avance del sistema completo, en lockstep en el peor caso posible,
@@ -105,7 +105,7 @@ module cache_control
 		data_wr = core_data_wr;
 		index_rd = core_index;
 
-		state_wr = INVALID;
+		state_wr = INVALID; //FIXME: debería ser 'bx
 		write_data = 0;
 		write_state = 0;
 
@@ -117,14 +117,17 @@ module cache_control
 		send_inval = 0;
 
 		set_reply = 0;
+		inval_reply = 0;
 		core_waitrequest = 1;
 
 		in_data_ready = !in_hold_valid;
 
 		unique case (state)
 			ACCEPT: begin
-				if (last_hop && !in_hold.read)
+				if (last_hop && !in_hold.read) begin
+					inval_reply = in_hold_valid;
 					in_data_ready = 1;
+				end
 
 				if (accept_snoop)
 					index_rd = in_hold.index;
@@ -239,7 +242,7 @@ module cache_control
 			mem_begin = 1;
 
 		// Colisiones de bus 
-		retry = (mem_end_read && (write_data || write_state)) || (mem_wait && mem_begin);
+		retry = (mem_read_end && (write_data || write_state)) || (mem_wait && mem_begin);
 
 		// Nótese la diferencia con un assign, ya que send puede cambiar más abajo
 		lock_line = send;
@@ -258,7 +261,7 @@ module cache_control
 		end
 
 		index_wr = index_rd;
-		if (mem_end_read) begin
+		if (mem_read_end) begin
 			tag_wr = mem_tag;
 			index_wr = mem_index;
 
@@ -289,8 +292,7 @@ module cache_control
 					next_state = SNOOP;
 				else if (in_hold_valid && last_hop && in_hold.read)
 					next_state = REPLY;
-				else if ((core_read || core_write) && !reply_wait
-				          && (!locked || (may_send && !unlock_line)))
+				else if ((core_read || core_write) && !wait_reply && (!locked || may_send))
 					next_state = CORE;
 
 				if (out_stall && !out_data_ready)
@@ -313,6 +315,7 @@ module cache_control
 			out_stall <= 0;
 
 			locked <= 0;
+			wait_reply <= 0;
 
 			mem_read <= 0;
 			mem_write <= 0;
@@ -336,6 +339,12 @@ module cache_control
 			if (unlock_line)
 				locked <= 0;
 
+			if (send)
+				wait_reply <= 1;
+
+			if (inval_reply || mem_read_end)
+				wait_reply <= 0;
+
 			if (mem_end) begin
 				mem_read <= 0;
 				mem_write <= 0;
diff --git a/rtl/cache/defs.sv b/rtl/cache/defs.sv
index 2566058..6fdb719 100644
--- a/rtl/cache/defs.sv
+++ b/rtl/cache/defs.sv
@@ -7,7 +7,8 @@ typedef logic[127:0] line;
 
 // Choca con typedef en core/uarch.sv
 `ifndef WORD_DEFINED
-typedef logic[31:0]  word;
+typedef logic[29:0] ptr;
+typedef logic[31:0] word;
 `define WORD_DEFINED
 `endif
 
diff --git a/rtl/cache/routing.sv b/rtl/cache/routing.sv
index 4857e08..45e0296 100644
--- a/rtl/cache/routing.sv
+++ b/rtl/cache/routing.sv
@@ -5,7 +5,7 @@ module cache_routing
 	input  logic       clk,
 	                   rst_n,
 
-	input  word        core_address,
+	input  ptr         core_address,
 	input  logic       core_read,
 	                   core_write,
 	input  line        core_writedata_line,
@@ -39,7 +39,6 @@ module cache_routing
 
 	word core_address_line;
 	logic cached, cache_mem, transition;
-	addr_mbz mbz;
 	addr_io_region io;
 
 	enum int unsigned
@@ -52,7 +51,7 @@ module cache_routing
 	assign cached = io == 3'b000;
 	assign cache_mem = cache_mem_read || cache_mem_write;
 
-	assign {io, core_tag, core_index, core_offset, mbz} = core_address;
+	assign {io, core_tag, core_index, core_offset} = core_address;
 	assign core_address_line = {io, core_tag, core_index, 4'b0000};
 	assign core_readdata_line = cached ? data_rd : mem_readdata;
 
diff --git a/rtl/cache/sram.sv b/rtl/cache/sram.sv
index 2e6c6ce..986c09b 100644
--- a/rtl/cache/sram.sv
+++ b/rtl/cache/sram.sv
@@ -23,9 +23,9 @@ module cache_sram
 
 	localparam DEPTH = 1 << $bits(addr_index);
 
-	line data_file[DEPTH];
-	addr_tag tag_file[DEPTH];
-	line_state state_file[DEPTH];
+	line data_file[DEPTH] /*verilator public*/;
+	addr_tag tag_file[DEPTH] /*verilator public*/;
+	line_state state_file[DEPTH] /*verilator public*/;
 
 	always_ff @(posedge clk) begin
 		if (write_data) begin
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index 0226cbf..38b0130 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -6,6 +6,7 @@
 
 // Choca con typedef en cache/defs.sv
 `ifndef WORD_DEFINED
+typedef logic[29:0] ptr;
 typedef logic[31:0] word;
 `define WORD_DEFINED
 `endif
@@ -14,7 +15,6 @@ typedef logic[3:0]  reg_num;
 typedef logic[2:0]  cp_opcode;
 typedef logic[15:0] reg_list;
 typedef logic[63:0] dword;
-typedef logic[29:0] ptr;
 
 `define R14 4'b1110
 `define R15 4'b1111