Make the fetch stage use the bus arbiter

2 files changed, 33 insertions, 20 deletions

diff --git a/conspiracion.qsf b/conspiracion.qsf
index e8371d3..86add17 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -213,27 +213,27 @@ set_location_assignment PIN_AF14 -to clk_clk
 
 set_global_assignment -name SEARCH_PATH rtl
 
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/shifter.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/and.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/isa.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/shifter.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/map.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/shifter.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/isa.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles.sv
 
 set_global_assignment -name QSYS_FILE platform.qsys
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv
@@ -242,4 +242,4 @@ set_global_assignment -name SDC_FILE conspiracion.sdc
 
 
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index a8e197b..81d9883 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -12,19 +12,19 @@ module arm810
 	output word  bus_data_wr
 );
 
-	logic stall, prefetch_flush;
+	logic stall, prefetch_flush, insn_start;
 	word insn;
-	ptr fetch_insn_pc;
+	ptr fetch_insn_pc, insn_addr;
 
 	core_fetch #(.PREFETCH_ORDER(2)) fetch
 	(
 		.branch(explicit_branch | wr_pc),
 		.flush(0), //TODO
 		.target(wr_pc ? wr_value[29:0] : branch_target),
-		.addr(bus_addr),
-		.fetched(bus_ready),
-		.fetch_data(bus_data_rd),
-		.fetch(bus_start),
+		.addr(insn_addr),
+		.fetched(insn_ready),
+		.fetch_data(insn_data_rd),
+		.fetch(insn_start),
 		.insn_pc(fetch_insn_pc),
 		.*
 	);
@@ -112,4 +112,17 @@ module arm810
 		.c(c_shifter)
 	);
 
+	//TODO
+	ptr data_addr;
+	logic data_start, data_write, data_ready;
+	word data_data_rd, data_data_wr;
+
+	logic insn_ready;
+	word insn_data_rd;
+
+	core_mmu mmu
+	(
+		.*
+	);
+
 endmodule