diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-09 07:46:44 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-09 07:46:44 -0600 |
| commit | b6af88a04f281483e8fef961eb4d0b2bf60ee7f0 (patch) | |
| tree | 4f88eef705d4a4fdbe3a23cce57ca61677d3e726 | |
| parent | 9965c5ef7abfbafebeb1afaed6d20cd0f38e0200 (diff) | |
Connect bus master to 50MHz reference clock
Diffstat (limited to '')
| -rw-r--r-- | platform.qsys | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/platform.qsys b/platform.qsys index 5d21cde..1d0fd4f 100644 --- a/platform.qsys +++ b/platform.qsys @@ -1111,6 +1111,7 @@ <parameter name="defaultConnection" value="false" /> </connection> <connection kind="clock" version="20.1" start="clk_0.clk" end="master_1.clk" /> + <connection kind="clock" version="20.1" start="clk_0.clk" end="master_0.clock" /> <connection kind="clock" version="20.1" start="clk_0.clk" end="pll_0.refclk" /> <connection kind="clock" @@ -1129,11 +1130,6 @@ version="20.1" start="pll_0.outclk0" end="hps_0.f2h_sdram0_clock" /> - <connection - kind="clock" - version="20.1" - start="pll_0.outclk1" - end="master_0.clock" /> <connection kind="clock" version="20.1" start="pll_0.outclk2" end="vram.clk" /> <connection kind="clock" |