From b6af88a04f281483e8fef961eb4d0b2bf60ee7f0 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 9 Nov 2022 07:46:44 -0600
Subject: Connect bus master to 50MHz reference clock

---
 platform.qsys | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/platform.qsys b/platform.qsys
index 5d21cde..1d0fd4f 100644
--- a/platform.qsys
+++ b/platform.qsys
@@ -1111,6 +1111,7 @@
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection kind="clock" version="20.1" start="clk_0.clk" end="master_1.clk" />
+ <connection kind="clock" version="20.1" start="clk_0.clk" end="master_0.clock" />
  <connection kind="clock" version="20.1" start="clk_0.clk" end="pll_0.refclk" />
  <connection
    kind="clock"
@@ -1129,11 +1130,6 @@
    version="20.1"
    start="pll_0.outclk0"
    end="hps_0.f2h_sdram0_clock" />
- <connection
-   kind="clock"
-   version="20.1"
-   start="pll_0.outclk1"
-   end="master_0.clock" />
  <connection kind="clock" version="20.1" start="pll_0.outclk2" end="vram.clk" />
  <connection
    kind="clock"
-- 
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