From 6fa92c4aab7b212de79c023ef8320a9cc6fd45c3 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 2 Apr 2023 00:00:44 -0600 Subject: [PATCH] to.verilog: fix always_ff sensitivity list --- hdlConvertorAst/to/verilog/stm.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hdlConvertorAst/to/verilog/stm.py b/hdlConvertorAst/to/verilog/stm.py index 28f3676..7b7dd99 100644 --- a/hdlConvertorAst/to/verilog/stm.py +++ b/hdlConvertorAst/to/verilog/stm.py @@ -92,7 +92,7 @@ class ToVerilog2005Stm(ToVerilog2005Expr): w("always_latch ") else: raise ValueError(proc.trigger_constrain) - if tr is None: + if tr in (None, HdlStmProcessTriggerConstrain.FF): w("@(") for last, item in iter_with_last(sens): self.visit_iHdlExpr(item) -- 2.38.4