| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | __init__.py | 0 | logplain |
| -rw-r--r-- | dsp_mul.sv | 1301 | logplain |
| -rw-r--r-- | mem_interconnect.sv | 3826 | logplain |
| d--------- | models | 143 | logplain |
| d--------- | sim | 1257 | logplain |
| d--------- | top | 279 | logplain |
| -rw-r--r-- | verilator.hpp | 621 | logplain |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |