| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | control_flow.c | 637 | logplain |
| -rw-r--r-- | control_flow.py | 117 | logplain |
| -rw-r--r-- | fibonacci.c | 143 | logplain |
| -rw-r--r-- | fibonacci.py | 252 | logplain |
| -rw-r--r-- | hazards.S | 257 | logplain |
| -rw-r--r-- | hazards.py | 167 | logplain |
| -rw-r--r-- | link.ld | 483 | logplain |
| -rw-r--r-- | mult.c | 209 | logplain |
| -rw-r--r-- | mult.py | 215 | logplain |
| -rw-r--r-- | shifts.S | 295 | logplain |
| -rw-r--r-- | shifts.py | 97 | logplain |
| -rwxr-xr-x | sim.py | 7773 | logplain |
| -rw-r--r-- | stack.S | 247 | logplain |
| -rw-r--r-- | stack.py | 241 | logplain |
| -rw-r--r-- | start.S | 274 | logplain |
| -rw-r--r-- | tarea2.S | 943 | logplain |
| -rw-r--r-- | tarea2.py | 403 | logplain |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |